
MAX1434
Octal, 10-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
4
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ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 1.8V, VOVDD = 1.8V, VCVDD = 3.3V, VGND = 0V, external VREFIO = 1.24V, CREFIO = 0.1F, CREFP = 10F, CREFN = 10F,
fCLK = 50MHz (50% duty cycle), VDT = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 2, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input at GND
5
Input Leakage Current
DIIN
Input at AVDD
80
A
Input Capacitance
DCIN
5pF
DIGITAL INPUTS (PLL_, LVDSTEST, DT, SLVS, PD,
T/B)
Input Logic-High Voltage
VIH
0.8 x
VAVDD
V
Input Logic-Low Voltage
VIL
0.2 x
VAVDD
V
Input at GND
5
Input Leakage Current
DIIN
Input at AVDD
80
A
Input Capacitance
DCIN
5pF
LVDS OUTPUTS (OUT_P, OUT_N), SLVS/
LVDS = 0
Differential Output Voltage
VOHDIFF
RTERM = 100
250
450
mV
Output Common-Mode Voltage
VOCM
RTERM = 100
1.125
1.375
mV
Rise Time (20% to 80%)
tRL
RTERM = 100
, CLOAD = 5pF
350
ps
Fall Time (80% to 20%)
tFL
RTERM = 100
, CLOAD = 5pF
350
ps
SLVS OUTPUTS (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, FRAMEN), SLVS/
LVDS = 1, DT = 1
Differential Output Voltage
VOHDIFF
RTERM = 100
205
mV
Output Common-Mode Voltage
VOCM
RTERM = 100
220
mV
Rise Time (20% to 80%)
tRS
RTERM = 100
, CLOAD = 5pF
320
ps
Fall Time (80% to 20%)
tFS
RTERM = 100
, CLOAD = 5pF
320
ps
POWER-DOWN
PD Fall to Output Enable
tENABLE
(Note 7)
100
ms
PD Rise to Output Disable
tDISABLE
20
ns
POWER REQUIREMENTS
AVDD Supply Voltage Range
VAVDD
1.7
1.8
1.9
V
OVDD Supply Voltage Range
VOVDD
1.7
1.8
1.9
V
CVDD Supply Voltage Range
VCVDD
1.7
1.8
3.6
V
PD = 0
348
390
PD = 0, DT = 1
348
mA
AVDD Supply Current
IAVDD
fIN = 19.3MHz
at -0.5dBFS
PD = 1, power-down,
no clock input
1.54
mA
PD = 0
78
100
PD = 0, DT = 1
100
mA
OVDD Supply Current
IOVDD
fIN = 19.3MHz
at -0.5dBFS
PD = 1, power-down,
no clock input
566
A
CVDD Supply Current
ICVDD
CVDD is used only to bias ESD-protection
diodes on CLK input, Figure 2
0mA
Power Dissipation
PDISS
fIN = 19.3MHz at -0.5dBFS
767
882
mW